This invention relates to design techniques for designing ICs and particularly to optimization of setup time and hold time in ICs by restructuring the data and clock logics for timing optimization.
An integrated circuit chip (herein referred to as an xe2x80x9cICxe2x80x9d or xe2x80x9cchipxe2x80x9d) comprises cells and connections between cells supported by a substrate. A cell is a group of one or more circuit elements, such as transistors, capacitors and other basic circuit elements, grouped to perform a function. Each cell may have one or more pins, which in turn may be connected to one or more pins of other cells by wires. A net comprises circuitry coupling two or more pins. A typical IC includes a large number of cells and requires complex wire connections between the cells. A typical chip has thousands, tens of thousands and even hundreds of thousands of pins which are connected in various combinations.
The IC components are fabricated on a substrate or wafer by layering different materials. The design of an IC transforms a circuit description into a geometric description known as a layout. Due to the large number of components and exacting details required by fabrication processes, the layout of an IC is ordinarily designed using a computer. The performance of an IC is computed during the design process using computed delays of the cells, including the setup and hold time delays. The setup time is the time duration that a data signal is required to be available at the input of a cell before the clock signal transition. The hold time is the time duration that a data signal is required to be stable after the clock signal transition. Delay of either of these events can affect IC performance.
In the design of integrated circuits, it has become increasingly accepted that more useful skews and higher IC operating frequencies may be realized by simultaneous optimization of the clock logics and the data logics. For example, see U.S. application Ser. No. 09/885,589 filed Jun. 19, 2001 for xe2x80x9cMethod of Integrating Clock Tree Synthesis and Timing Optimization for an Integrated Circuit Designxe2x80x9d by Pavisic et al. and U.S. application Ser. No. 09/991,574 filed Nov. 20, 2001 for xe2x80x9cChanging Clock Delays in an Integrated Circuit for Skew Optimizationxe2x80x9d by Lu et al., both assigned to the same assignee as the present invention. Not only does this approach provide an additional optimization potential, but it also greatly simplifies the design flow. However there is a potential problem with this approach. More particularly, simultaneous optimization of clock logics and data logics may increase the hold time violations when optimizing setup time.
One technique to resolve timing violation problems is addressed in a synthesis tool described in U.S. application Ser. No. 09/677,475 filed Oct. 2, 2000 for xe2x80x9cMethod and Apparatus for Timing Driven Resynthesisxe2x80x9d by Zolotykh et al. and assigned to the same assignee as the present invention. While the Zolotykh et al. technique has been quite successful, there nevertheless exists a risk that hold time violations can be increased. There is, therefore, a need for a cost-effective technique to optimize the setup time without significantly increasing the hold time violations.
The present invention is directed to a technique permitting trade off of the priorities of both setup and hold time optimization targets while minimizing the cost function at each optimization step.
In accordance with one embodiment of the present invention, setup and hold time violations are optimized by resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing the data and clock logics coupled to pins of the integrated circuit to optimize hold time violations.
More particularly, setup time violations are optimized by resynthesizing the clock logics of each pin having a setup time violation. The data logics are then resynthesized for each pin having a setup time violation. The clock logics are then again resynthesized for each pin having a setup time violation.
In preferred embodiments, the first step of resynthesis of the clock logics to optimize setup time violations is performed by resynthesizing the data logics of pins having a maximal setup time violation to optimize the maximal setup time violation. The clock logics are resynthesized for first and second groups of pins to optimize the setup time violation of each pin of the first group without controlling the hold time, and to optimize the setup time violation of each pin of the second group while controlling the hold time.
Preferably, the hold time violations are optimized by resynthesizing the data logics of each pin having a hold time violation. The clock logics are then resynthesized for each pin having a hold time violation.
In preferred embodiments, a plurality of cost functions are calculated based on setup and hold time violations, are selectively applied to the resynthesis processes.
In other embodiments, the process is carried out using a computer operating under the control of program code.